A 12nm Finfet Technology Featuring 2nd Generation Finfet For Low Power And High Performance Applications

H.C. Lo,D. Choi,Y. Hu, Y. Shen,Y. Qi,J. Peng,D. Zhou, M. Mohan,C. Yong, H. Zhan, H. Wei,X. He,D. Kang, A. Sirman, Y. Wang, H. Zang, S.Y. Mun, A. Vinslava,W.H. Chen,C. Gaire, J. Liu,X. Dou, Y. Shi,P. Zhao,B. Zhu, A. Jha,X. Zhang, X. Wan, E. Lavigne, C. Kyono,M. Togo, J. Versaggi,H. Yu, O. Hu,J.G. Lee, S. B. Samavedam, D.K. Sohn

2018 IEEE SYMPOSIUM ON VLSI TECHNOLOGY（2018）

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摘要

We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area) improvement over 14LPP. 12LP enables >10% area reduction including a 7.5T library and 16% power reduction at fixed frequency or a 15% performance improvement at given leakage over 14LPP with comparable reliability and yield. In addition, SRAMs benefit from a 30% leakage reduction at the same Iread. 12LP extends the 14nm technology with compelling performance and area scaling.

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关键词

FinFET, 12LP, 7.5T library, PPA

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