32-Bit 4 × 4 Bit-Slice RSFQ Matrix Multiplier

IEEE Transactions on Applied Superconductivity(2018)

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摘要
A 32-bit 4 × 4 bit-slice rapid single-flux-quantum (RSFQ) matrix multiplier is proposed. The multiplier mainly consists of bit-slice multipliers and bit-slice adders. The multiplication of unsigned integer matrices is implemented by control signals. The matrix multiplier used synchronous concurrent-flow clocking. The results show that a 16-bit bit-slice processing has the least latency at 10 GHz.
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关键词
Adders,Delays,Clocks,Microprocessors,Computer architecture,Pipelines,Hardware
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