A lightweight X-masking scheme for IoT designs

The emerging Internet-of-Things (IoT) paradigm creates a new market for very small and cost-sensitive chips. Design costs must be as low as possible in order to be competitive. In this context, the 1-pin test has proven to be a beneficial way to significantly reduce test costs. However, the incorporated signature generation requires an X-free design, which is not always possible (e.g. due to timing exceptions in transition tests). Available X-masking approaches target large circuits and are therefore not suitable due to their large area overhead or because they require additional pins. In this paper, we present a solution to this business case problem. A new X-masking scheme with very small area overhead and the ability for usage during 1-pin test is proposed. We present experimental results on industrial designs. Those experiments show for the first time that transition tests with X-values in their response can be applied during 1-pin test. The method has been successfully verified on silicon and is already being applied during productive test application.