Lauroc: "A New Electronically Cooled Line-Terminating Preamplifier For The Atlas Liquid Argon Calorimeter Upgrade"

2016 IEEE NUCLEAR SCIENCE SYMPOSIUM, MEDICAL IMAGING CONFERENCE AND ROOM-TEMPERATURE SEMICONDUCTOR DETECTOR WORKSHOP (NSS/MIC/RTSD)(2016)

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摘要
The readout electronics of the ATLAS Liquid Argon (LAr) Calorimeter (for the phase II of the high luminosity Large Hadron Collider at CERN) will be replaced and integrated in a single chip in order to reduce the power dissipation by an order of magnitude and to provide fully digital data. The cornerstone of the circuit is the preamplifier which is very demanding in terms of low noise, large dynamic range (at least 16 bits) and precise input impedance (25 or 50 Ohms) to terminate the cables from the detector. An innovative architecture is proposed to fulfill these requirements: a current conveyer and a single resistor are imbedded as feedback of a low noise amplifier. This architecture ensures accurate input impedance over a large frequency range (100MHz) as well as input current range (10mA). The noise remains low thanks to this architecture which acts as an "electronically cooled" resistor out of an ultra-low noise amplifier (0.4 n V / root Hz). This design provides at the same time a current and a voltage output which could be used as high and low gain paths. An anti-saturation system is embedded to switch off the high gain when is saturated."LAUROC", which stands for Liquid Argon Upgrade Read-Out Chip, represents the first step of this new chip development designed in TSMC 130nm technology by OMEGA. The chip was sent in fabrication in April and is expected during summer to be tested in laboratory on a test board developed by LAL group.
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accurate input impedance,input current range,electronically cooled resistor,ultra-low noise amplifier,high gain paths,low gain paths,anti-saturation system,Liquid Argon Upgrade Read-Out,chip development,LAUROC,electronically cooled line-terminating preamplifier,ATLAS liquid argon calorimeter upgrade,readout electronics,high luminosity Large Hadron Collider,single chip,power dissipation,fully digital data,dynamic range,at least 16 bits,precise input impedance,innovative architecture,current conveyer,single resistor,word length 16.0 bit,frequency 100.0 MHz,current 10.0 mA,voltage 0.4 V,size 130.0 nm
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