A Novel Generic Low Latency Hybrid Architecture for Parallel Pipelined Radix-2^k Feed Forward FFT

The need for high throughput low latency FFT implementation in communication systems has led to the evolution of different architectures with multiple parallel inputs and outputs. This paper presents a novel generic hybrid architecture for parallel pipelined radix-2 ^k FFT using FF (Feed Forward) architecture which is also known as MDC (Multi-path Delay Commutator). The proposed architecture offers a new FFT data buffering algorithm for a parallel pipelined normal order inputs FFT using MDC. Our architecture offers a great reduction in latency up to 25% when compared to state of the art parallel pipelined FFT architectures. This latency reduction is achieved as the total number of buffers needed for an N-point FFT doesn't exceed 1.5N and approaches N in some cases. In addition to that, the proposed architecture doesn't depend on the implementation of butterfly (BF) or rotation operation. Although the presented work is for radix-2 ^k FFT, it can be generalized to radix-r.