A Reconfigurable DLL-Based Digital-to-Time Converter Using Charge Pump Current Interpolation and Digital Predistortion Linearization

This brief presents a digital-to-time converter (DTC) based on a reconfigurable delay-locked loop that employs dual feedback taps and interpolation at the output of two charge pumps biased with programmable complementary currents from a current digital-to-analog converter (I-DAC) to achieve fine delay tuning. Through selection of the feedback and output delay line taps, the 65-nm CMOS prototype can be configured to achieve different specs, such as a 24.5 ps delay span with a 0.46 ps maximum delay step and 1.33 ps maximum RMS jitter or a span of 244 ps with a 3.30 ps maximum step and 2.63 ps maximum RMS jitter when a 7-bit I-DAC and a 2 GHz input are used. A simple digital predistortion method to compensate for the inherent nonlinearity of the architecture is presented and experimentally shown to improve the worst-case integral nonlinearity from −14.3 LSB (−27.6 ps) to +1.79 LSB (+3.43 ps) for the 244 ps delay span case, and by 67%–88% at all taps for the same loop configuration. Excluding the I-DAC, which would require an estimated 0.2 mW, the DTC consumes 0.665 mW from a 1.25-V supply at 2 GHz and occupies an area of 46 $ {\mu }\text{m}\,\,{\times }$ 28 ${\mu }\text{m}$ .