A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties.

Kyuseung Han,Jae-Jin Lee,Woojoo Lee,Jinho Lee

IEEE Design & Test（2019）

引用 4|浏览29

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摘要

Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.

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关键词

Field programmable gate arrays,Debugging,Monitoring,IP networks,Network-on-chip,System-on-chip,Receivers

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