Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach.

Recent work has established Lagrangian relaxation (LR) based gate sizing as state-of-the-art providing the best power reduction with low run time. Gate sizing has limited potential to reduce the power when the timing constraints are tight. By adjusting the arrival times of clock signals (clock skew scheduling), the timing constraints can be relaxed facilitating more power reduction. Previous LR attempts at simultaneous gate sizing and skew scheduling solved a minimum-cost network flow problem for updating the Lagrange multipliers in each LR iteration, and for optimality assumed continuous sizes with convex delay models. We propose an alternative approach, modifying a LR discrete gate sizing formulation with table lookup non-convex delay models, which are more accurate for modern process technologies. For the Lagrange multiplier update, we use a projection heuristic that is much faster than solving the minimum cost network flow problem. On the ISPD 2012 gate sizing contest benchmark suite, our proposed approach outperforms the previous min-cost flow based approach by saving 5.3% more power and is 70x faster. Compared to sizing alone with the state-of-the-art LR gate sizer, skew scheduling with sizing saves 19.7% more power with a small runtime penalty.