A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier.

Md Shakil Akter,Rohan Sehgal,Frank M. L. van der Goes,Kofi A. A. Makinwa,Klaas Bult

IEEE Journal of Solid-State Circuits（2018）

引用 14|浏览3

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摘要

This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push-pull structure with a “split-capacitor” biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier's ...

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关键词

Capacitors,Calibration,Linearity,Capacitance,Power dissipation,Transistors,Clocks

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