A case for hardware-supported sub-cache line accesses

Largely, the performance of main-memory databases is limited by the growing memory gap. To be efficient, a DBMS cannot waste any bandwidth. However, this is exactly the case when 64-byte cache lines are transferred but only parts of these are used. We present a cache simulator that measures this waste, show that current databases waste up to 70% of the available bandwidth, and discuss a new gather instruction with sub-cache line access granularity that could reduce this waste.