Hybrid Quick Error Detection: Validation and Debug of SoCs through High-Level Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2019)

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摘要
Validation and debug challenges of system-on-chips (SoCs) are getting increasingly difficult. As we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Hence, it is essential to address the validation and debug of hardware accelerators. High-level synthesis (HLS...
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关键词
Computer bugs,Hardware,Testing,C++ languages,Software,Integrated circuit modeling,Tools
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