FPGA based seizure detection and control for brain computer interface

The paper presents a brain computer interface system for patient monitoring to detect and correct seizure. About 4–7% of people are suffering from seizure and there are only less medical attention available. The objective of the work described in this paper is to detect and cure seizure automatically without physician intervention. The therapeutic device is a modeled chip using Field Programmable Gate Array Logic and SoC in which the size of the instrument is small. The EEG signals of the brain are recorded using scalp electrodes and converted to digital data. The EEG signal is preprocessed using quadrature spline wavelet transform. FPGA implementation of quadrature spline wavelet transform filter was done with Baugh Wooley and array multiplier. From the results it is found that the power and logic elements are improved when Baugh Wooley multiplier is used. But when delay is compared array multiplier has better performance. The preprocessed data is feature extracted using double stage pattern search method where the seizure event is detected. Once the seizure is detected, the seizure control block is activated. It controls the seizure in few seconds. For seizure detection and correction, adaptive methods and hardware simulators are used. The performance and efficiency is compared for various devices using Quartus in FPGA cyclone II and III.