Design and operational assessment of an intra-cell hybrid L2 cache

This paper deals with the integration of several emerging technologies (embedded DRAM (eDRAM) and Phase Change Memory (PCM)) with SRAM to leverage their operational features and achieve a hybrid L2 cache for improvements in density and power consumption. A novel hybrid cache replacement and migration policy is proposed; a hybrid macrocell is also designed using a different number of eDRAM, PCM and SRAM cells (referred to as the memory ratio). Two cache models at architectural and circuit levels are presented for intra-cell operation. A 4-way hybrid cache is considered throughout this manuscript as example. By simulating applications benchmarks, comparison and analysis on different replacement and migration policies and the impact of the memory ratio are provided to assess the proposed hybrid cache design.