Embedded Vernier TDC with sub-nano second resolution using fractional-N PLL

Measurement（2017）

引用 8|浏览1

暂无评分

摘要

•Novel implementation technique for high-resolution TDC in FPGAs.•New area of application for fractional-N PLLs.•Sub-nanosecond resolution demonstrated.•Vernier TDC theory outlined.•A potential resolution limit of 10ps is suggested.

查看译文

关键词

Time-to-digital converter,Phase-locked loop,Vernier,FPGA,Fractional-N PLL

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要