A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver.

Saurabh Saxena,Guanghua Shu,Romesh Kumar Nandwana,Mrunmay Talegaonkar,Ahmed Elkholy,Tejasvi Anand,Woo-Seok Choi,Pavan Kumar Hanumolu

IEEE Journal of Solid-State Circuits（2017）

引用 18|浏览83

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摘要

Design techniques to improve energy efficiency of serial link transceivers are presented. Power consumption is reduced by using: low-power clock generation, recovery, and distribution schemes; charge-based circuits to implement analog front-end and samplers/flip-flops; and a partially segmented voltage-mode (VM) output driver. An LC-oscillator based digital phase-locked loop (PLL) is used to gener...

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关键词

Clocks,Transceivers,Phase locked loops,Bandwidth,Jitter,Delays,Power demand

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