An area-efficient digitally-assisted DC canceling loop for high sensitivity UHF RFID receiver

An area-efficient digitally-assisted DC canceling loop is presented for high sensitivity single-chip UHF RFID readers. The proposed loop suppresses the DC blocker in RFID receivers by 41 dB with the aid of negative feedback. A delta-sigma modulator with 67dB dynamic range is implemented in the loop to enhance the sensitivity of the receiver. A reconfigurable digital loop filter with low cut off frequency is designed for compact chip area. The DC canceling loop is fabricated in a 0.13µm CMOS process. It occupies a silicon area of 1.69mm ² and dissipates 24.3mW from a 1.2V supply. The proposed loop is demonstrated in an RFID reader prototype. A −70dBm sensitivity of the reader is measured in the presence of +5dBm self-jammer.