Channel-Stacked NAND Flash Memory With Tied Bit-Line and Ground Select Transistor

In this letter, a channel-stacked array with tied bit-line (BL) and ground select transistor (GST) is proposed to access each layer independently without additional string select transistors (SSTs) to a conventional planar NAND array. The proposed structure can maximize memory density, since additional SSTs are not required for layer selection and the placement of BLs/word lines is similar to that...