Fabrication and characterization of a low parasitic capacitance and low-stress Si interposer for 2.5D integration

This paper presents the fabrication and characterization of a low parasitic capacitance and low-stress Si interposer for 2.5-D/3-D integration of stress sensitive MEMS devices. The glass reflow process is utilized to isolate Si posts (through silicon interposer) from Si substrate of a low resistivity to form vertical electrical interconnection. A process is developed and a dummy Si interposer is f...