Low Cost And Highly Manufacturable Mol/Beol Constructs In 22fdsoi Technology For High Performance And Low Power Applications

Navneet Jain,Juhan Kim, Sushama Davar,Shibly Ahmed,Jeff Kim, Arif Siddiqi,Thomas Herrmann,Joerg Winkler, Frank Barth, Jens Pika,Michael Zier,Jamie Schaeffer,Mahbub Rashed, Anurag Mittal, James Blatchford,Sunil Machha, Siva Krisha Potta, Atul Kumar Kashyap, Sravan Kumar Tekuru, Ram Prasad Gopannagari

2018 IEEE 2ND ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2018)（2018）

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摘要

A highly optimized 22FDSOI Logic Architecture for Power, Performance, Area (PPA) and cost is presented in this paper. Unique features of FDSOI technology including channel strain based PFET transistor performance enhancement are further advanced with innovative low cost MOL/BEOL based special constructs. The new constructs allow a highly optimized 8T-CNRX library design. Based on this architecture, PPA advantage is demonstrated over competing bulk and FinFET technologies. This Logic Architecture offers FinFET like performance with 28nm bulk like simple MOL and cost structure.

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关键词

22FDSOI technology,low Power applications,channel strain,PFET,22FDSOI Logic Architecture,MOL-BEOL constructs,8T-CNRX library design,FinFET technologies,size 28.0 nm

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