Cost-efficient Sub-Lithographic Patterning with Tilted-Ion Implantation (TII)
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)(2018)
关键词
tilted-ion implantation,TII,size 10.0 nm,Monte Carlo process simulations,LER,linear hard-mask features,nonlinear hard-mask features,cost-efficient sub-lithographic patterning,line-edge roughness,Moore's Law,sub-lithographic patterning technique
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