Incoming and Inline Defectivity Control Solutions for Silicon Carbide Manufacturing

Si l icon car b ide (Si C ) man u f act u ring is transitioning from 4 inch wafers to 6 inch wafers for production line devices. The main obstacle for SiC manufacturing high yield is defect control. Defectiveness inline control is well established for silicon power device. However, there are two main challenges related to SiC technology. The first challenge is incoming 4H-SiC substrates defectivity and epi layer crystallographic defects. The second challenge is inline defect detection at process steps such as implantation and annealing activation [,]. Defect detection and classification are difficult with current defect inspection tools because of substrate transparency at visible light, color variation, roughness, and wafers’ high warpage. In addition, SiC device integration has been requesting specific optimization. In this paper, collaboration studies have been done to develop solutions to these challenges. Yield correlation analyses have validated the process control flow set to address these two major challenges and to enable the fast ramp of the 6” production line of SiC devices.