Scalable Construction of Clock Trees with Useful Skew and High Timing Quality

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2019)

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摘要
Clock trees can be constructed based on static arrival time constraints or dynamic implied skew constraints. Dynamic implied skew constraints allow the full timing margins to be utilized. However, the dynamic skew constraints require a high run-time complexity to be evaluated. In contrast, static arrival time constraints are more restrictive but can be evaluated in constant time. Consequently, the...
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关键词
Clocks,Time factors,Wires,Delays,Topology,Space exploration
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