Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1147-1160, 2018.
As very large scale integration technology scales to deep submicron, design for interconnections becomes increasingly challenging. The traditional bus routing follows a sequential bit-by-bit order, and few works explicitly target interbit regularity for signal groups via multilayer topology selection. To overcome these limitations, we pre...More
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