Circuit Timing Analysis and Optimization under Flexible Flip-flop Timing Model

Most of static timing analyses today are based on conventional fixed flip-flop timing models, in which every flip-flop is assumed to have a fixed clock-to-Q delay. However, since the setup and hold skews affect the clock-to-Q delay in reality, many researchers have paid attention to the flexible flip-flop timing property in circuit timing analysis and optimization. Nevertheless, the existing works have failed in solving the problem of exactly formulating the sequences of timing dependency among the skews and delays over time. In this work, we solve the problem, specifically, (1) proposing a mathematical formulation to solve the problem, (2) applying our solution to the analysis of a given circuit as well as (3) to the clock skew scheduling problems, and (4) proposing a speedup technique. Through experiments with benchmark circuits, it is demonstrated that our method can rectify improper or unoptimized results drawn from the previous approach. It is also shown that our speedup technique is able to shorten run times significantly with very little loss of optimality.