Inductance Modeling of Interconnections in 3-D Stacked-Chip Packaging

Chenbing Qu,Yang Liu,Xiaoxian Liu,Zhangming Zhu

IEEE Microwave and Wireless Components Letters（2018）

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摘要

This letter explores the inductance of interconnections including through-silicon vias (TSVs) and redistribution layers (RDLs) in 3-D stacked-chip packaging. It is described that the common summing method of partial inductances will result in some deviations from the full inductance. Then, the inductances of TSVs and RDLs are, respectively, calculated and are verified by a commercial electromagnet...

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关键词

Through-silicon vias,Inductance,Error analysis,Solid modeling,Metals,Integrated circuit interconnections,Integrated circuit modeling

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