Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance

IEEE Transactions on Electron Devices(2018)

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摘要
Negative capacitance field effect transistor (NCFET) is designed in 5-nm FinFET node, which simultaneously meets the low-power and high-performance targets of ION and IOFF at Vdd = 0.5 V and Vdd = 0.23 V, respectively, while the international roadmap for devices and systems (ITRS 2.0) projected Vdd is 0.65 V for both. The impact of power supply and parasitic capacitance on the performance of NCFET...
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关键词
Logic gates,Integrated circuit modeling,Parasitic capacitance,Iron,FinFETs,Mathematical model
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