A 7nm Cmos Technology Platform For Mobile And High Performance Compute Application

S. Narasimha, B. Jagannathan, A. Ogino,D. Jaeger,Brian J. Greene,C. Sheraw, K. Zhao, B. S. Haran,Unoh Kwon, A. K. M. Mahalingam,B. Kannan, B. Morganfeld,J. Dechene,C. Radens, A. Tessier,A. Hassan, H. Narisetty,I. Ahsan, M. Aminpur, C. An, M. Aquilino, A. Arya,Rod Augur, N. Baliga, R. Bhelkar, G. Biery, A. Blauberg, N. Borjemscaia, A. Bryant,L. Cao, V. Chauhan, M. Chen, L. Cheng, J. Choo,C. Christiansen,Tao Chu,B. Cohen, R. Coleman, D. Conklin, S. Crown, A. da Silva,D. Dechene, G. Derderian, S. Deshpande, G. Dilliway, K. Donegan,Manfred Eller, Y. Fan, Q. Fang, A. Gassaria,R. Gauthier,S. Ghosh, G. Gifford, T. Gordon, M. Gribelyuk, G. Han, J.H. Han, K. Han,M. Hasan, J. Higman,J. Holt, L. Hu, L. Huang,C. Huang,T. Hung,Y. Jin, J. Johnson, S. Johnson,V. Joshi, M. Joshi, P. Justison, S. Kalaga,T. Kim, W. Kim, R. Krishnan, B. Krishnan,K. Anil, M. Kumar, J. Lee,R. Lee, J. Lemon, S.L. Liew, P. Lindo,M. Lingalugari, M. Lipinski, P. Liu,Jinping Liu, S. Lucarini,W. Ma, E. Maciejewski, S. Madisetti, A. Malinowski,J. Mehta, C. Meng, S. Mitra, C. Montgomery,H. Nayfeh, T. Nigam, G. Northrop, K. Onishi, C. Ordonio, M. Ozbek,Rohit Pal, Sanjay Parihar,O. Patterson, E. Ramanathan,I. Ramirez,R. Ranjan, J. Sarad, V. Sardesai, S. Saudari, C. Schiller,Biswanath Senapati, C. Serrau, N. Shah,T. Shen,H. Sheng,J. Shepard, Y. Shi, M.C. Silvestre,D. Singh, Z. Song, J. Sporre,P. Srinivasan, Z. Sun,A. Sutton, R. Sweeney, K. Tabakman, M. Tan,X. Wang, E. Woodard, G. Xu, D. Xu, T. Xuan, Y. Yan, J. Yang,K.B. Yeap, M. Yu,A. Zainuddin, J. Zeng, K. Zhang, M. Zhao, Y. Zhong, Rick Carter, Chung-hsun Lin,Stephan Grunow, C. Child, M. Lagus,Robert Fox, E. Kaste, G. Gomba, Srikanth Samavedam, P. Agnello, D. K. Sohn

2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2017）

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摘要

We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [13]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um(2). This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MIP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.

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关键词

HD 6-T bitcell size,optical patterning techniques,SAQP,SADP,mobile applications,mobile performance compute application,BEOL metallization,logic density,CMOS technology platform

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