A novel concurrent error detection technique for the fast Fourier transform implemented in SRAM-based FPGAs

A novel Concurrent Error Detection (CED) technique for the complex Fast Fourier Transform (FFT) implemented in SRAM based Field Programmable Gate Arrays (FPGA) is presented in this paper. This technique compares one of the inputs to a linear combination of the outputs, avoiding complex multiplications. Hence its computational complexity and resource usage are lower than that of the Parseval Sum of Squares (SoS) or other CED techniques applied to this algorithm. In order to test its performance, bit-flips have been injected in the FPGA configuration bits. The technique achieves high error detection rates with fewer unnecessary reconfigurations than SoS, which makes it suitable for applications in which circuit size and availability are critical.