Explicit layout pattern density controlling based on transistor-array-style
Midwest Symposium on Circuits and Systems Conference Proceedings(2017)
摘要
An aggressive controlling for layout pattern density is becoming essential for the manufacturability of advanced processes. Focusing on analog layout under severe density constraints, this paper provides a novel idea that layout generation and verification are co-working on a density-aware format. Our idea follows a transistor-array(TA)-style of analog layout where unit-transistors of the same channel-size are used to form an array. In this style, we can explicitly control the layout pattern density by changing array pitch, stretching poly gates or widening diffusion of unit-transistors. We present a framework to enumerate feasible design parameters satisfying density and DRC constraints. In a design case of an OPAMP layout in a 65nm process, we demonstrate that our framework can converge the design in much fewer iterations compared with a traditional style layout by manual drawing.
更多查看译文
关键词
analog layout,density constraint,transistor-array
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络