Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology

Shang-Yun Hou,W. Chris Chen,Clark Hu,Christine Chiu, K. C. Ting, T. S. Lin, W. H. Wei,W. C. Chiou, Vic J. C. Lin,Victor C. Y. Chang, C.-T. Wang,Chung-Cheng Wu,Douglas Yu

IEEE Transactions on Electron Devices（2017）

引用 124|浏览13

暂无评分

摘要

State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200 mm2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accom...

查看译文

关键词

Silicon,Through-silicon vias,Metals,Stress,Bandwidth,Routing

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要