A 0.3V VDDmin 4+2T SRAM for searching and in-memory computing using 55nm DDC technology

Qing Dong,Supreet Jeloka,Mehdi Saligane,Yejoong Kim,Masaru Kawaminami,Akihiko Harada,Satoru Miyoshi,David T. Blaauw,Dennis Sylvester

2017 Symposium on VLSI Circuits（2017）

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摘要

A 4+2T SRAM is proposed that offers searching and logic functions. The cell uses the N-well as the write wordline (WL) and eliminates the access transistors. Decoupled read paths enable reliable multi-word activation for in-memory Boolean logic functions. The SRAM can reconfigure to BCAM/TCAM for searching operations, with 0.13fJ/search/bit at 0.35V. Forty test chips in 55nm deeply depleted channel (DDC) technology achieve worst-case 0.3 V VDDmin.

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关键词

SRAM,N-well,write wordline,access transistors,decoupled read paths,multi-word activation,in-memory Boolean logic functions,BCAM-TCAM,deeply depleted channel technology,DDC technology,voltage 0.35 V,size 55 nm,voltage 0.3 V

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