Spin coating modeling and planarization using fill patterns for advanced packaging technologies

An empirical model is proposed for the dielectric spin coating (DSC) and curing process applied to existing underlying topographies in redistribution layers (RDLs). Test structures that represent a wide range of underlying feature widths, spacings, and heights are designed and fabricated. These are coated with multiple thicknesses of polyimide, and their surfaces are profiled and analyzed. An empirical model based on spatial filtering over underlying features is developed, with model parameters fit to coatings over a single feature for each set of process parameters. The model predicts post-coating thicknesses at the chipscale. Comparisons between predictions and experimental results show an RMS error of 4.4% of the feature heights when averaged over each region profiled. Finally, fill and cheesing patterns are designed and new test structures are simulated using these patterns. Simulation results suggest that global variations can be made as small as desired using these fill and cheesing patterns, limited only by the minimum allowable feature size and resolution.