In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices

Chi Lim Tan,Simone Lavizzari,Pieter Blomme,L. Breuil, Guglielma Vecchio,Farid Sebaai,Vasile Paraschiv,Zheng Tao,Bart Schepers,Laura Nyns,Antony Peter,Harold Dekkers,Patrick Ong,Diana Tsvetanova, K. Devriendt,Lieve Teugels,Nancy Heylen, Tom Raymaekers,Nico Jossart, Pasquale Mennella,Romain Delhougne,Senthil Vadakupudhu Palayam,A. Arreghini,Geert Van den bosch,A. Furnemont

2017 IEEE International Memory Workshop (IMW)（2017）

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摘要

An in-depth analysis of gate stack enhancements that enable multi-Gb 3D NAND products is performed. Alternative charge trapping layer, enhanced tunnel oxide based on the VariOT concept and metal gate with Al2O3 high-k liner have been proposed and evaluated. The most promising solutions were successfully integrated in 3D devices. Integration challenges of the replacement gate approach, required to have metal gate in 3D NAND, are also analyzed and discussed in detail.

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关键词

3D NAND enabler analysis,gate stack integration,gate stack demonstration,3D devices,gate stack enhancement analysis,multiGb 3D NAND products,charge trapping layer,enhanced tunnel oxide,VariOT concept,metal gate,high-k liner,replacement gate approach,Al2O3

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