HBM (High Bandwidth Memory) DRAM Technology and Architecture

2017 IEEE International Memory Workshop (IMW)(2017)

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摘要
HBM (High Bandwidth Memory) is an emerging standard DRAM solution that can achieve breakthrough bandwidth of higher than 256GBps while reducing the power consumption as well. It has stacked DRAM architecture with core DRAM dies on top of a base logic die, based on the TSV and die stacking technologies. In this paper, the HBM architecture is introduced and a comparison of its generations is provided. Also, the packaging technology and challenges to address reliability, thermal dissipation capability, maximum allowable package sizes, and high throughput stacking solutions are described. Test technology and testability features are discussed for KGSD and 2.5D SiP.
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关键词
HBM DRAM technology,high bandwidth memory,power consumption reduction,stacked DRAM architecture,core DRAM dies,base logic die,die stacking technologies,packaging technology,reliability,thermal dissipation capability,maximum allowable package sizes,high throughput stacking solutions,test technology,testability features,KGSD,2.5D SiP
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