Proposed Architecture for Low Power and Area Efficient Edge Combiner

In this paper we proposed architecture of edge combiner circuit that consumes very low power as compared to a conventional XOR edge multiplier design. The proposed edge combiner's architecture is well suited for frequency multiplier applications. The proposed edge combiner is tested for input frequencies of up to 250MHz. The design is implemented on 65nm complementary metal oxide semiconductor (CMOS) process. The simulation results show that the total power consumption of proposed design is 7.68 times less than the total power of conventional XOR edge combiner. The switching power of proposed design is only 8% of the total power which was 25% in conventional edge combiner. Area of the edge combiner is 7.8nm i.e. 3.33 times less than the XOR edge combiner.