Co-development of complementary technology and modified-CPL family for organic digital integrated circuits

We present a novel logic family alternative to classic CMOS logic and its experimental demonstration for digital application of organic electronics. The proposed logic family is a modified version of the complementary pass-transistor logic (mCPL), which allows use of a stronger transistor (in our case the p-FET) to provide more of the current required to switch the capacitance in the device. We report the integration and characterization of this new class of gates and compare them with the equivalent CMOS structures. The characterization of inverters shows improved tolerance to process variation, up to 2.5× better delay, and 1.7× smaller area for the mCPL devices. Comparison of NOR and NAND gates shows 1.8× and 4.1× reduced gate delay. A 3× reduced energy consumption per operation is also simulated. The improved performance of the mCPL design makes it an alternative architecture for logic application of organic electronics.