Layout-Dependent Effect Evaluation Of Transistor Array-Style Phase Locked Loop

The transistor array(TA)-style is a layout methodology where an analog layout is configured on the pattern such that unit-transistors of the same size form an array. It contributes to an easy implementation of design automation, and it also serves a design to mitigate the process variability in 90nm beyond. In this work, utilizing a phase locked loop(PLL) circuit as a motif, we verify the relationship between the fine processes and TA-style. We generate the layouts of the PLL based on the TA-style on 0.6um, 180nm, 65nm in three processes, and compare them with respect to the area and the post-layout simulation results of the control voltage of the VCO. Besides, we also generate a custom layout in 0.6um process, and report the comparison result with the TA-style one.