Transaction level and RTL modeling of an architecture for network data compression within ethernet switches in large file transfer scenarios

Storage networks have become major components of modern data centers. In some applications, moving huge amounts of data between servers and storage devices really challenges the architecture of the data center. Therefore, there is a growing interest in data compression applied to reduce the volume of data transfers in storage networks. Because of the latency, hardware is often preferred over software based compression. However, the administration overhead, and material cost required to furnish every server and storage device with a compression card is prohibitive. In this work, the architecture and implementation of a compressor-decompressor is presented. Then, the data flow is analyzed using Transfer Level Modeling in SystemC. The conclusions of that analysis are used to design an Ethernet switch in which data is compressed and decompressed as it flows between servers and storage devices in the network. The proposed system implements resource sharing, transparent use, and minimal latency on top of the benefits of data compression. This work is meant to be extended to other application beyond data compression, opening a new field for hardware-based accelerators, that will be located in the network rather that into individual nodes.