A 12Bit 800MS/s time-interleaving pipeline ADC in 65nm CMOS

In this paper, a dual-channel 12-Bit 800MS/S time-interleaving pipeline ADC is presented. Each pipeline channels share a common sample-and-hold amplifier either to eliminate the timing mismatch or to diminish the residue charge. Multiple voltage supply is utilized, which makes using wideband single stage cascoded OTA possible. An on-chip input buffer is applied to reduce the kick-back noise from the sampling network. Fabricated in a 65nm process, the ADC achieves a SNDR of 61.39dB and a SFDR of 67.54dB with a 251MHz input at 800MS/s. Total power consumed is 720mW.