Memory Design Using One-Transistor Gain Cell on SOI : Proposal of a Novel RAM Cell of 4F^2 Size
Technical report of IEICE. ICD（2002）
关键词
DRAM chips,MOS memory circuits,cellular arrays,circuit simulation,integrated circuit design,integrated circuit measurement,integrated circuit modelling,silicon-on-insulator,0.18 micron,40 ns,512 kbit,DRAM,MOS process,SOI,Si,access time,array driving method,device simulation,hardware measurement,memory design,nondestructive readout,one-transistor gain cell,selective write,
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