Heavy Ion Characterization of Temporal-, Dual- and Triple Redundant Flip-Flops Across a Wide Supply Voltage Range in a 65 nm Bulk CMOS Process

In this paper, we investigate the single event upset (SEU) response of five D flip-flops (DFFs) employing temporal redundancy, dual redundancy, and triple modular redundancy (TMR), across a wide supply voltage range. The DFFs were designed and fabricated in a low-power commercial 65 nm bulk CMOS process and were tested using heavy ions with linear energy transfer (LET) between 5.1 MeV - cm2/mg and...