Ti and NiPt/Ti liner silicide contacts for advanced technologies

Praneet Adusumilli,Emre Alptekin,Mark Raymond,Nicolas L. Breil, F. Chafik,Christian Lavoie, D. Ferrer,S. Jain,V. Kamineni,Ahmet S. Ozcan, S. Allen, J. J. An, V. S. Basker, R. Bolam,Huiming Bu,Jin Cai,J. Demarest,Bruce B. Doris, E. Engbrecht,S. Fan, J. Fronheiser,Oleg Gluschenkov,Dechao Guo, B. Haran, D. Hilscher,Hemanth Jagannathan,D. Kang, Y. Ke,J. Kim,Siyuranga O. Koswatta, Anil Kumar,A. Labonte, R. Lallement, W.-H. Lee, Y. Lee,Jing Li,C-H Lin,B. Liu,Zuoguang Liu,N. Loubet, N. Makela,Shogo Mochizuki, B. Morgenfeld, S. Narasimha, T. Nesheiwat,Hiroaki Niimi,C. Niu, M. Oh, C. Park, J. Rice, V. Sardesai, J. Shearer,C. Sheraw, C. Tran,Gen Tsutsui,Henry K. Utomo, K. Wong,R. Xie,Tenko Yamashita,Y. Yan, C. Yeh, M. Yu,Noah Zamdmer, N. Zhan, B. Zhang,Vamsi Paruchuri, C. Goldberg, W. Kleemeier, S. Stiffler, R. Divakaruni, W. Henson

2016 IEEE Symposium on VLSI Technology（2016）

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摘要

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

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关键词

liner silicide contacts,source-drain contacts,3D FinFET devices,n-FET,p-FET,metallization process,dopant concentrations,epitaxy,size 14 nm,NiPt-Ti,SiGe

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