On-chip interconnect trends, challenges and solutions: How to keep RC and reliability under control

Zs. Tokei,Ivan Ciofi,Ph. Roussel,P. Debacker,Praveen Raghavan,M. H. van der Veen,N. Jourdan,Christopher J. Wilson,V. Vega Gonzalez,C. Adelmann, L. Wen,Kristof Croes,O.Varela Pedreira K. Moors,Mikhail Krishtab,Silvia Armini,Jürgen Bömmels

2016 IEEE Symposium on VLSI Technology（2016）

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摘要

Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome these challenges simultaneous optimization of novel metallization schemes, new materials, circuit and system level approaches are required.

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关键词

on-chip interconnect trends,reliability,technology scaling,metallization optimization,system level approach,circuit level approach,RC delay

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