Timing characterizations of device and CPU-like circuit to ensure process reliability

Existing methodology and stress conditions are ideal for process benchmarking but might not be sufficient under fierce competition between advanced technology development approaches. In this paper, the importance of timing delay characterization in both device and circuit level is demonstrated and emphasized. Due to the difficulties of having accurate aging model for product level simulation during early stage of process development, silicon to simulation (S2S) correlation should be established in circuit level. Experiments in this study cover from discrete device, ring oscillator (RO) and a circuit block from ARM CPU. Based on the extensive results, the characterization of timing margin is highly recommended. So, early warnings of circuit reliability risk can be obtained to save major detours during technology development.