Implementation of memory stacking on logic controller by using 3DIC 300mm backside TSV process integration

Shang-Chun Chen,Pei-Jer Tzeng, Yu-Chen Hsm,Chung-Chih Wang,Po-Chih Chang, Jui-Chm Chen,Yiu-Hsiang Chang,Tsuen-Sung Chen,Tzu-Chien Hsu,Hsiang-Hung Chang,Chau-Jie Zhan,Chia-Hsin Lee,Yung-Fa Chou,Ding-Ming Kwai,Tzu-Kun Ku,Pei-Hua Wang,Wei-Chung Lo

2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)（2016）

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摘要

Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical measurement data and functional logic circuit test show the practicability of BTSV integration.

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关键词

3DIC backside TSV process integration,memory stacking,logic controller,backside via-last TSV,industry cooperation,mass production business,DRAM stacking structure,key enabling process technology,thin wafer handling,electrical measurement data,functional logic circuit test,size 300 mm,size 45 nm,size 65 nm

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