A 10Gb/s Analog Adaptive Equalizer for Backplanes

Serial links via backplane channels suffer from severe signal integrity problems which are normally caused by channel imperfections, such as flat loss, frequency-dependent loss, reflection, etc. Particularly, the frequency-dependent loss causes ISI(Inter-Symbol-Interference) at signal waveforms. Therefore, adaptive equalizing techniques have been exploited in many products to facilitate the ISI problem. In this paper, we present an analog adaptive equalizer circuit designed in a CMOS process. It achieves 10Gb/s data transmission through a long 34-inch backplane channel(or transmission line). The post-layout simulations demonstrate jitter with 10mW power dissipation. The core of the adaptive equalizer occupies the area of .