An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration
Journal of microelectronics and electronic packaging(2011)
摘要
This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.
更多查看译文
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要