An Effective Approach for Building Low-Power General Activity-Driven Clock Trees

It is known that clock gating is a useful technique to reduce power consumption. Based on activity patterns of modules, previous works utilized AND gates to construct activity-driven gated clock trees. Recently, it was pointed out OR gates can be used at the bottom level for further power saving. In this paper, we present a general activity-driven clock tree structure in which both AND gate and OR gate can be utilized at any node. Based on this general structure, an effective synthesis algorithm is proposed. Benchmark data show that the proposed approach can reduce 11.3% clock power consumption.