An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition

Compressive sensing (CS) is a novel signal processing technology to reconstruct the sparse signal at sub-Nyquist rate. Orthogonal matching pursuit (OMP) is one of the most widely used signal reconstruction algorithms. However, the least square problem (LSP) in OMP algorithm limits its performance. This paper presents a fast CS reconstruction algorithm implemented on field-programmable gate array (FPGA) using OMP. The proposed algorithm adopts an incremental QR decomposition (QRD) method to efficiently solve the LSP. The incremental QRD is further optimized to eliminate the square root operation to facilitate hardware implementation. The proposed architecture avoiding the complex square root unit mainly consists of some more basic computing units, where the computing process is broken down into several simple operations to map to the corresponding hardware for pipelining. The proposed implementation based on Xilinx Kintex-7 FPGA exploits the parallelism by a well-planned workload schedule and reaches an optimal tradeoff between the latency and frequency. The experimental results demonstrate that the proposed architecture can run at a frequency of 210 MHz with a reconstruction time of 238 $\mu \text{s}$ for 36-sparse 1024-length signal, which improves the signal reconstruction speed by $1.43\times $ compared to the state-of-the-art implementations.