Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs

Automotive innovation is driving the need for built-in reliability, safety and security solutions and architectural design to mitigate emerging threats and, particularly, the number of possible sources affecting arisen failures. In other words, the problem can be stated as reduction of failure rate-one of the most common metrics used for reliability evaluation. Soft errors in memories will be considered in the paper. Their FIT rate is significantly more than the typical FIT rate for a hard reliability failure. A special technique is described to assess the soft error rate and to mitigate the effects of soft errors via error correcting codes (ECC). Ways to calculate the failure rate in the presence of ECC are considered jointly with different ECC solutions. Since ECC also incurs a significant area overhead, a problem arises how to choose memories in SoC which should have ECC in order to meet the reliability requirements and, at the same time, the area constraints. In this paper, an efficient ECC planning solution is presented to solve the problem. The experimental results are adduced which show the advantages of the proposed solution.